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19-3063; Rev 0; 1/04
Ultra-Low-Power, 12-Bit, Voltage-Output DACs
General Description
The MAX5530/MAX5531 are single, 12-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering Rail-to-Rail(R) buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 6A, making them desirable for lowpower and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18A. The MAX5530/MAX5531 use a 3-wire serial interface that is compatible with SPITM, QSPITM, and MICROWIRETM. At power-up, the MAX5530/MAX5531 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that must be off during power-up. The zero-scale outputs enable glitchfree power-up. The MAX5530 accepts an external reference input. The MAX5531 contains an internal reference and provides an external reference output. Both devices have forcesense-configured output buffers. The MAX5530/MAX5531 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin QFN package and are guaranteed over the extended -40C to +85C temperature range. For 10-bit compatible devices, refer to the MAX5520/ MAX5521 data sheet. For 8-bit compatible devices, refer to the MAX5510/MAX5511 data sheet.
Features
Ultra-Low 6A Supply Current Shutdown Mode Reduces Supply Current to 0.18A (max) Single +1.8V to +5.5V Supply Small 4mm x 4mm x 0.8mm Thin QFN Package Flexible Force-Sense-Configured Rail-to-Rail Output Buffers Internal Reference Sources 8mA of Current (MAX5531) Fast 16MHz 3-Wire SPI-/QSPI-/MICROWIRECompatible Serial Interface TTL- and CMOS-Compatible Digital Inputs with Hysteresis Glitch-Free Outputs During Power-Up
MAX5530/MAX5531
Ordering Information
PART MAX5530ETC MAX5531ETC TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 12 Thin QFN-EP* 12 Thin QFN-EP*
*EP = Exposed paddle (internally connected to GND).
Applications
Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory or Field Programmable Voltage and Current Sources Industrial Process Control and Remote Industrial Devices Remote Data Conversion and Monitoring Chemical Sensor Cell Bias for Gas Monitors Programmable Liquid Crystal Display (LCD) Bias
4 5 DIN 3 CS SCLK 1 2
Pin Configuration
TOP VIEW
FB 12 N.C. 11 OUT 10
9 8 7
GND VDD N.C.
MAX5530 MAX5531
6 N.C.
Selector Guide
PART MAX5530ETC MAX5531ETC REFERENCE External Internal TOP MARK AACS AACT
REFIN (MAX5530) N.C. REFOUT(MAX5531)
THIN QFN
Rail-to-Rail is a registered trademark of Nippon Motorola, Inc. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUT to GND ...............................................-0.3V to (VDD + 0.3V) FB to GND ..................................................-0.3V to (VDD + 0.3V) SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V) REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) Thin QFN (derate 16.9mW/C above +70C ..............1349mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ..................................................... +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 12 4 4 0.2 0.2 1 1 2 GE VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V 2 2 4 PSRR N INL VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V Guaranteed monotonic, VDD = 5V, VREF = 3.9V Guaranteed monotonic, VDD = 1.8V, VREF = 1.2V Offset Error (Note 2) Offset-Error Temperature Drift Gain Error (Note 3) Gain-Error Temperature Coefficient GE VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V VOS VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V 1.8V VDD 5.5V 12 4 4 0.2 0.2 1 1 2 2 2 4 4 4 8 8 1 LSB 1 20 20 mV V/C LSB ppm/C 85 4 4 8 8 1 LSB 1 20 20 mV V/C LSB ppm/C dB Bits LSB TYP MAX UNITS Bits LSB STATIC ACCURACY (MAX5530 EXTERNAL REFERENCE) Resolution N Integral Nonlinearity (Note 1) INL VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V Guaranteed monotonic, VDD = 5V, VREF = 4.096V Guaranteed monotonic, VDD = 1.8V, VREF = 1.024V Offset Error (Note 2) Offset-Error Temperature Drift Gain Error (Note 3) Gain-Error Temperature Coefficient Power-Supply Rejection Ratio Resolution Integral Nonlinearity (Note 1) STATIC ACCURACY (MAX5531 INTERNAL REFERENCE) VOS VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V
Differential Nonlinearity (Note 1)
DNL
Differential Nonlinearity (Note 1)
DNL
2
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Power-Supply Rejection Ratio REFERENCE INPUT (MAX5530) Reference-Input Voltage Range Reference-Input Impedance REFERENCE OUTPUT (MAX5531) No external load, VDD = 1.8V Initial Accuracy VREFOUT No external load, VDD = 2.5V No external load, VDD = 3V No external load, VDD = 5V Output-Voltage Temperature Coefficient Line Regulation VTEMPCO TA = -40C to +85C (Note 4) VREFOUT < VDD - 200mV (Note 5) 0 IREFOUT 1mA, sourcing, VDD = 1.8V, VREF = 1.2V Load Regulation 0 IREFOUT 8mA, sourcing, VDD = 5V, VREF = 3.9V -150A IREFOUT 0, sinking 0.1Hz to 10Hz, VREFOUT = 3.9V Output Noise Voltage 10Hz to 10kHz, VREFOUT = 3.9V 0.1Hz to 10Hz, VREFOUT = 1.2V 10Hz to 10kHz, VREFOUT = 1.2V Short-Circuit Current (Note 6) Capacitive Load Stability Range Thermal Hysteresis Reference Power-Up Time (from Shutdown) Long-Term Stability DAC OUTPUT (OUT) Capacitive Driving Capability CL VDD = 5V, VOUT set to full scale, OUT shorted to GND, source current VDD = 5V, VOUT set to 0V, OUT shorted to VDD, sink current VDD = 1.8V, VOUT set to full scale, OUT shorted to GND, source current VDD = 1.8V, VOUT set to 0V, OUT shorted to VDD, sink current 1000 65 65 mA 14 14 pF VDD = 5V VDD = 1.8V (Note 7) (Note 8) REFOUT unloaded, VDD = 5V REFOUT unloaded, VDD = 1.8V 1.197 1.913 2.391 3.828 1.214 1.940 2.425 3.885 12 2 0.3 0.3 0.2 150 600 50 450 30 14 0 to 10 200 5.4 4.4 200 mA nF ppm ms ppm/ 1khrs VP-P 1.231 1.967 2.459 3.941 30 200 2 2 V/A ppm/C V/V V VREFIN RREFIN Normal operation In shutdown 0 4.1 2.5 VDD V M G SYMBOL PSRR CONDITIONS 1.8V VDD 5.5V MIN TYP 85 MAX UNITS dB
MAX5530/MAX5531
Short-Circuit Current (Note 6)
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3
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS Coming out of shutdown (MAX5530) DAC Power-Up Time Coming out of standby (MAX5531) Output Power-Up Glitch FB_ Input Current DIGITAL INPUTS (SCLK, DIN, CS) 4.5V VDD 5.5V Input High Voltage VIH 2.7V < VDD 3.6V 1.8V VDD 2.7V Input Low Voltage Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time SR Positive and negative (Note 10) 0.1 to 0.9 of full scale to within 0.5 LSB (Note 10) 0.1Hz to 10Hz Output Noise Voltage 10Hz to 10kHz POWER REQUIREMENTS Supply Voltage Range VDD VDD = 5V MAX5530 Supply Current (Note 9) IDD MAX5531 VDD = 3V VDD = 1.8V VDD = 5V VDD = 3V VDD = 1.8V VDD = 5V Standby Supply Current Shutdown Supply Current IDDSD IDDPD (Note 9) (Note 9) VDD = 3V VDD = 1.8V 1.8 2.6 2.6 3.6 5.3 4.8 5.4 3.3 2.8 2.4 0.05 5.5 4 4 5 7.0 7.0 7.0 4.5 4.0 3.5 0.25 A A A V VDD = 5V VDD = 1.8V VDD = 5V VDD = 1.8V 10 660 80 55 620 476 VP-P V/ms s VIL IIN CIN 4.5V VDD 5.5V 2.7V < VDD 3.6V 1.8V VDD 2.7V (Note 9) 0.05 10 2.4 2.0 0.7 x VDD 0.8 0.6 0.3 x VDD 0.5 V A pF V CL = 100pF VDD = 5V VDD = 1.8V VDD = 1.8V to 5.5V MIN TYP 3 3.8 0.4 10 10 mV pA ms MAX UNITS
4
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low CS Pulse-Width High SCLK Rise to CS Rise Hold Time CS Fall to SCLK Rise Setup Time SCLK Fall to CS Fall Setup CS Rise to SCK Rise Hold Time SYMBOL fSCLK tDS tDH tCH tCL tCSW tCSH tCSS tCSO tCS1 CONDITIONS MIN 0 15 0 24 24 100 0 20 0 20 TYP MAX 16.7 UNITS MHz ns ns ns ns ns ns ns ns ns
MAX5530/MAX5531
TIMING CHARACTERISTICS (VDD = 4.5V TO 5.5V)
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low CS Pulse-Width High SCLK Rise to CS Rise Hold Time CS Fall to SCLK Rise Setup Time SCLK Fall to CS Fall Setup CS Rise to SCK Rise Hold Time SYMBOL fSCLK tDS tDH tCH tCL tCSW tCSH tCSS tCSO tCS1 CONDITIONS MIN 0 24 0 40 40 150 0 30 0 30 TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS (VDD = 1.8V TO 5.5V)
Note 1: Linearity is tested within codes 96 to 4080. Note 2: Offset is tested at code 96. Note 3: Gain is tested at code 4095. FB is connected to OUT. Note 4: Guaranteed by design. Not production tested. Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that the package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10k in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5530) or VREF = 3.9V (MAX5531).
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5
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5530), VREF = 3.9V (MAX5531), TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5531)
MAX5530 toc01
SUPPLY CURRENT vs. TEMPERATURE (MAX5531)
MAX5530 toc02
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5531)
MAX5530 toc03
10 9 8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0
10 9 8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0
1000 SHUTDOWN SUPPLY CURRENT (nA)
100
10
1
0.1 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
STANDBY SUPPLY CURRENT vs. TEMPERATURE (MAX5531)
MAX5530 toc04
SUPPLY CURRENT vs. CLOCK FREQUENCY
MAX5530 toc05
SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE
4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ALL DIGITAL INPUTS SHORTED TOGETHER
MAX5530 toc06 MAX5530 toc09
5.0 4.5 STANDBY SUPPLY CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60 VREF = 1.9V VREF = 1.2V VREF = 3.9V VREF = 2.4V
1000 CS = LOGIC LOW CODE = 0 SUPPLY CURRENT (A) VDD = 5V 100
5.0
10
VDD = 1.8V
1 85 0.01 0.1 1 10 100 1000 10000 100000 TEMPERATURE (C) FREQUENCY (kHz)
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V)
INL vs. INPUT CODE (VDD = VREF = 1.8V)
MAX5530 toc07
INL vs. INPUT CODE (VDD = VREF = 5V)
1 0 -1 -2 -3 -4 -5 DNL (LSB) INL (LSB)
MAX5530 toc08
DNL vs. INPUT CODE (VDD = VREF = 1.8V)
0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10
2 1 0 INL (LSB) -1 -2 -3 -4 -5 0
2
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE
6
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5530), VREF = 3.9V (MAX5531), TA = +25C, unless otherwise noted.)
DNL vs. INPUT CODE (VDD = VREF = 5V)
MAX5530 toc10
OFFSET VOLTAGE vs. TEMPERATURE
MAX5530 toc11
GAIN-ERROR CHANGE vs. TEMPERATURE
0.4 GAIN-ERROR CHANGE (LSB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 VDD = 5V VREF = 3.9V
MAX5530 toc12
0.20 0.15 0.10 DNL (LSB) 0.05 0 -0.05 -0.10 -0.15 0
1.0 0.8 0.6 OFFSET VOLTAGE (mV) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 VDD = 5V VREF = 3.9V
0.5
500 1000 1500 2000 2500 3000 3500 4000 4500 DIGITAL INPUT CODE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
DIGITAL FEEDTHROUGH RESPONSE
MAX5530 toc13
DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT
MAX5530 toc14
DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT
1.9435 DAC OUTPUT VOLTAGE (V) 1.9430 1.9425 1.9420 1.9415 1.9410 1.9405 VDD = 5.0V DAC CODE = MIDSCALE VREF = 3.9V
MAX5530 toc15
0.6050 CS 5V/div SCLK 5V/div DIN 5V/div OUT 50mV/div VDD = 1.8V DAC CODE = MIDSCALE VREF = 1.2V
1.9440
ZERO SCALE
DAC OUTPUT VOLTAGE (V)
0.6048
0.6046
0.6044
0.6042
20s/div
0.6040 -1000-800 -600 -400 -200 0 200 400 600 800 1000 DAC OUTPUT CURRENT (A)
1.9400 -10 -8 -6 -4 -2 0 2 4 6 8 10 DAC OUTPUT CURRENT (mA)
DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX5530 toc16
DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
4.5 DAC OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VDD = 1.8V 0.01 0.1 1 10 100 VDD = 3V VDD = 5V VREF = VDD
CODE = MIDSCALE
MAX5530 toc17
OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 1.8V, VREF = 1.2V)
MAX5530 toc18
5 VREF = VDD CODE = MIDSCALE 4 OUTPUT VOLTAGE (V)
5.0
3
VDD = 5V
VOUT 200mV/div
2
VDD = 3V VDD = 1.8V
1
0 0.001
0.01
0.1
1
10
100
0 0.001
100s/div
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
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7
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5530), VREF = 3.9V (MAX5531), TA = +25C, unless otherwise noted.)
OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 5V, VREF = 3.9V)
MAX5530 toc19
OUTPUT MINIMUM SERIES RESISTANCE vs. LOAD CAPACITANCE
FOR NO OVERSHOOT MINIMUM SERIES RESISTANCE () VOUT 500mV/div 500 400 300 200 100 0 0.0001 0.001
MAX5530 toc20
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5530 toc21
600
VDD 2V/div
VOUT 10mV/div
200s/div
0.01
0.1
1
10
100
20ms/div
CAPACITANCE (F)
MAJOR CARRY OUTPUT VOLTAGE GLITCH (CODE 7FFh TO 800h) (VDD = 5V, VREF = 3.9V)
MAX5530 toc22
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
VDD = 5V REFERENCE OUTPUT VOLTAGE (V) 3.935 3.930 3.925 3.920 3.915 3.910 3.905 3.900 -40 -15 10 35 60 85
MAX5530 toc23
3.940
VOUT AC-COUPLED 5mV/div
100s/div
TEMPERATURE (C)
REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT
MAX5530 toc24
REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT
MAX5530 toc25
REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
1.21748 1.21746 1.21744 1.21742 1.21740 1.21738 1.21736 1.21734 1.21732 NO LOAD
MAX5530 toc26
1.220 VDD = 1.8V REFERENCE OUTPUT VOLTAGE (V) 1.219 1.218 1.217 1.216 1.215 1.214 -500 1500 3500 5500 7500 REFERENCE OUTPUT CURRENT (A)
3.92 VDD = 5V REFERENCE OUTPUT VOLTAGE (V) 3.91
1.21750 REFERENCE OUTPUT VOLTAGE (V)
3.90
3.89
3.88 -500 2000 4500 7000 9500 12,000 14,500 REFERENCE OUTPUT CURRENT (A)
1.21730 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
8
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5530), VREF = 3.9V (MAX5531), TA = +25C, unless otherwise noted.)
REFERENCE LINE-TRANSIENT RESPONSE (VREF = 1.2V)
MAX5530 toc27
REFERENCE LINE-TRANSIENT RESPONSE (VREF = 3.9V)
MAX5530 toc28
2.8V VDD 1.8V VREF 500mV/div
5.5V VDD 4.5V VREF 500mV/div 3.9V
100s/div
100s/div
REFERENCE LOAD TRANSIENT (VDD = 1.8V)
MAX5530 toc29
REFERENCE LOAD TRANSIENT (VDD = 5V)
MAX5530 toc30
REFOUT SOURCE CURRENT 0.5mA/div VREFOUT 500mV/div
REFOUT SOURCE CURRENT 0.5mA/div
VREFOUT 500mV/div 3.9V
200s/div
200s/div
REFERENCE LOAD TRANSIENT (VDD = 1.8V)
MAX5530 toc31
REFERENCE LOAD TRANSIENT (VDD = 5V)
MAX5530 toc32
REFOUT SINK CURRENT 50A/div
REFOUT SINK CURRENT 100A/div
VREFOUT 500mV/div
VREFOUT 500mV/div 3.9V
200s/div
200s/div
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9
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5530), VREF = 3.9V (MAX5531), TA = +25C, unless otherwise noted.)
REFERENCE PSRR vs. FREQUENCY
MAX5530 toc33
REFERENCE PSRR vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO (dB) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 1000 VDD = 5V
MAX5530 toc34
80 POWER-SUPPLY REJECTION RATIO (dB) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 VDD = 1.8V
80
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
MAX5530 toc35
REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
MAX5530 toc36
100V/div
100V/div
1s/div
1s/div
10
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs
Pin Description
PIN MAX5530 1 2 3 4 -- 5, 6, 7, 11 8 9 10 12 EP MAX5531 1 2 3 -- 4 5, 6, 7, 11 8 9 10 12 EP NAME CS SCLK DIN REFIN REFOUT N.C. VDD GND OUT FB Exposed Paddle Active-Low Digital-Input Chip Select Serial-Interface Clock Serial-Interface Data Input Reference Input Reference Output No Connection. Leave N.C. inputs unconnected (floating) or connected to GND. Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1F capacitor. Ground Analog Voltage Output Feedback Input Exposed Paddle. Connect EP to GND. FUNCTION
MAX5530/MAX5531
MAX5530 Functional Diagram
VDD REFIN
POWERDOWN CONTROL INPUT REGISTER SCLK DIN CS CONTROL LOGIC AND SHIFT REGISTER DAC REGISTER
12-BIT DAC OUT
MAX5530
FB
GND
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11
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
MAX5531 Functional Diagram
VDD
POWERDOWN CONTROL
2-BIT PROGRAMMABLE REFERENCE INPUT REGISTER DAC REGISTER
REF BUF
REFOUT
12-BIT DAC OUT
SCLK DIN CS
CONTROL LOGIC AND SHIFT REGISTER
MAX5531
FB
GND
Detailed Description
The MAX5530/MAX5531 single, 12-bit, ultra-low-power, voltage-output DACs offer Rail-to-Rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 6A (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18A. The MAX5531 includes an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When V DD is applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5530/MAX5531 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output amplifier inverting input is available). These devices come in a 4mm x 4mm thin QFN package.
Digital Interface
The MAX5530/MAX5531 use a 3-wire serial interface compatible with SPI, QSPI, and MICROWIRE protocols (Figures 1 and 2). The MAX5530/MAX5531 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. Data loads MSB first, D11-D0. The 16 bits consist of 4 control bits (C3-C0) and 12 data bits (D11-D0) (see Table 1). The control bits C3-C0 control the MAX5530/MAX5531, as outlined in Table 2. Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output. The double-buffered register configuration allows any of the following: * Loading the input registers without updating the DAC registers * Updating the DAC registers from the input registers * Updating all the input and DAC registers simultaneously
12
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs
Table 1. Serial Write Data Format
CONTROL MSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DATA BITS LSB D0
MAX5530/MAX5531
tCH SCLK tDS DIN tCS0 tCSS CS tCSW tCS1 C3 tDH C2 tCL
C1
D0 tCSH
Figure 1. Timing Diagram
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL BITS CS
DATA BITS COMMAND EXECUTED
Figure 2. Register Loading Diagram
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13
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Table 2. Serial-Interface Programming Commands
CONTROL BITS C3 0 0 0 0 0 0 0 0 1 C2 0 0 0 0 1 1 1 1 0 C1 0 0 1 1 0 0 1 1 0 C0 0 1 0 1 0 1 0 1 0 INPUT DATA D11-D0 XXXXXXXXXXXX 12-bit data -- -- -- -- -- -- 12-bit data FUNCTION No operation; command is ignored. Load input register from shift register; DAC register unchanged; DAC output unchanged. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Load DAC register from input register; DAC output updated; MAX5530 enters normal operation if in shutdown; MAX5531 enters normal operation if in standby or shutdown. Load input register and DAC register from shift register; DAC output updated; MAX5530 enters normal operation if in shutdown; MAX5531 enters normal operation if in standby or shutdown. Command reserved; do not use. Command reserved; do not use. MAX5530 enters shutdown; MAX5531 enters standby*. For the MAX5531, D11 and D10 configure the internal reference voltage (Table 3). MAX5530/MAX5531 enter normal operation; DAC output reflects existing contents of DAC register. For the MAX5531, D11 and D10 configure the internal reference voltage (Table 3). MAX5530/MAX5531 enter shutdown; DAC output set to high impedance. For the MAX5531, D11 and D10 configure the internal reference voltage (Table 3). Load input register and DAC register from shift register; DAC output updated; MAX5530 enters normal operation if in shutdown; MAX5531 enters normal operation if in standby or shutdown.
1 1 1 1
0 0 0 1
0 1 1 0
1 0 1 0
12-bit data -- -- D11, D10, XXXXXXXXXX
1
1
0
1
D11, D10, XXXXXXXXXX
1
1
1
0
D11, D10, XXXXXXXXXX
1
1
1
1
12-bit data
X = Don't care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown.
14
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Ultra-Low-Power, 12-Bit, Voltage-Output DACs
Power Modes
The MAX5530/MAX5531 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5531. The MAX5531 also offers a standby mode where all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. Standby mode also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation. Shutdown Mode The MAX5530/MAX5531 feature a software-programmable shutdown mode that reduces the typical supply current and the reference input current to 0.18A (max). Writing an input control word with control bits C[3:0] = 1110 places the device in shutdown mode (Table 2). In shutdown, the MAX5530 reference input and DAC output buffers go high impedance. Placing the MAX5531 into shutdown turns off the internal reference, and the DAC output buffers go high impedance. The serial interface remains active for all devices. Table 2 shows several commands that bring the MAX5530/MAX5531 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid. Note: For the MAX5531, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode. Standby Mode (MAX5531 Only) The MAX5531 features a software-programmable standby mode that reduces the typical supply current to 6A. Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. If the MAX5531 is coming out of standby, the power-up time from standby is required before the DAC outputs are valid. For the MAX5531, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation, followed immediately by the command to go into standby. Table 2 shows several commands that bring the MAX5531 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid.
MAX5530/MAX5531
Reference Input
The MAX5530 accepts a reference with a voltage range extending from 0 to VDD. The output voltage (VOUT) is represented by a digitally programmable voltage source as: VOUT = (VREF x N / 4096) x gain where N is the numeric value of the DAC's binary input code (0 to 4095), VREF is the reference voltage and gain is the externally set voltage gain for the MAX5530/ MAX5531. In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5G (typ).
Reference Output
Table 3. Reference Output Voltage Programming
D11 0 0 1 1 D10 0 1 0 1 REFERENCE VOLTAGE (V) 1.214 1.940 2.425 3.885
The MAX5531 internal voltage reference is software configurable to one of four voltages. Upon power-up, the default reference voltage is 1.214V. Configure the reference voltage using the D11 and D10 data bits (Table 3) when the control bits are as follows C[3:0] = 1100, 1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation.
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15
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Applications Information
1-Cell and 2-Cell Circuit
See Figure 3 for an illustration of how to power the MAX5530/MAX5531 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices makes the MAX5530/MAX5531 ideal for battery-powered applications.
Bipolar Output
The MAX5530 output can be configured for bipolar operation, as shown in Figure 8. The output voltage is given by the following equation: VOUT = VREF x [(NA - 2048) / 2048] where NA represents the numeric value of the DAC's binary input code. Table 5 shows digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 4.
Programmable Current Source
See the circuit in Figure 4 for an illustration of how to configure the MAX5530 as a programmable current source for driving an LED. The MAX5530 drives a standard NPN transistor to program the current source. The current source (I LED ) is defined in the equation in Figure 4.
Configurable Output Gain
The MAX5530/MAX5531 have a force-sense output, which provides a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5530/MAX5531 is specified in a unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components. An example of a custom fixed gain using the force-sense output of the MAX5530/MAX5531 is shown in Figure 9. In this example, R1 and R2 set the gain for VOUT. VOUT =[(VREFIN x NA) / 4096] x [1 + (R2 / R1)] where NA represents the numeric value of the DAC input code.
Voltage Biasing a Current-Output Transducer
See the circuit in Figure 5 for an illustration of how to configure the MAX5530 to bias a current output transducer. In Figure 5, the output voltage of the MAX5530 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R.
Self-Biased Two-Electrode Potentiostat Application
See the circuit in Figure 6 for an illustration of how to use the MAX5531 to bias a two-electrode potentiostat on the input of an ADC.
Unipolar Output
Figure 7 shows the MAX5530 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes.
VDD 1.8V VALKALINE 3.3V 2.2V VLITHIUM 3.3V 536k +1.25V 0.1F REFIN DAC VOUT VOUT (0.30mV / LSB)
MAX6006
(1A, 1.25V SHUNT REFERENCE)
0.01F
MAX5530
GND
V x NDAC VOUT = REFIN 4096 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
16
______________________________________________________________________________________
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
V+ LED ILED REFIN DAC VOUT 2N3904 FB REF OUT IF RF TO ADC WE SENSOR CE
DAC
TO ADC
MAX5530
FB
MAX5531
ILED = VREFIN x NDAC 4096 x R R
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
Figure 4. Programmable Current Source Driving an LED
BAND GAP
REFOUT TO ADC CL
REFIN
DAC VOUT VOUT VOUT = VBIAS + (IT x R)
Figure 6. Self-Biased Two-Electrode Potentiostat Application
MAX5530
FB TRANSDUCER VBIAS IT R
REFIN
DAC
OUT
V x NDAC VBIAS = REFIN 4096 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
MAX5530
FB VOUT = VREFIN x NA 4096
NA IS THE DAC INPUT CODE (0 TO 4095 DECIMAL).
Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer
Figure 7. Unipolar Output Circuit
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0001 0000 LSB 1100 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (4095/4096) +VREF (2049/4096) +VREF (2048/4096) = +VREF / 2 +VREF (2047/4096) +VREF (1/4096) 0V
Table 5. Bipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1111 0001 0000 1111 0001 0000 ANALOG OUTPUT +VREF (2047/2048) +VREF (1/2048) 0V -VREF (1/2048) -VREF (2047/2048) -VREF (2048/2048) = -VREF
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17
Ultra-Low-Power, 12-Bit, Voltage-Output DACs MAX5530/MAX5531
Power Supply and Bypassing Considerations
Bypass the power supply with a 0.1F capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed paddle to ground.
Layout Considerations
Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines.
10k
10k
MAX5530
REFIN VOUT
V+
DAC
OUT R2
VOUT
DAC REFIN OUT VFB R1
MAX5530
FB
Figure 8. Bipolar Output Circuit
Figure 9. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference
1.8V VDD 5.5V REFIN
DAC
VOUT VOUT H
CS1 MAX5530
FB SCLK DIN CS2
W
MAX5401 SOT-POT 100k 5PPM/C RATIOMETRIC TEMPCO L
VOUT =
VREFIN x NDAC 255 - NPOT 1+ 4096 255
(
)
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE.
Figure 10. Software-Configurable Output Gain
Chip Information
TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS
18 ______________________________________________________________________________________
Ultra-Low-Power, 12-Bit, Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5530/MAX5531
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
1
2
PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
24L QFN THIN.EPS

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